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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a op271 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 pin connections 16-pin sol (s-suffix) epoxy mini-dip (p-suffix) 8-pin hermetic dip (z-suffix) 8 7 6 5 1 2 3 4 out a ?in a v+ out b ?in b +in a +in b v? + ? + ? b a 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 nc = no connect nc ?in a nc +in a nc nc out b nc ?in b nc out a v+ v? nc +in b nc high-speed, dual operational amplifier features excellent speed: 8.5 v/ m s typ fast settling (0.01%): 2 m s typ unity-gain stable high-gain bandwidth: 5 mhz typ low input offset voltage: 200 m v max low offset voltage drift: 21 m v/ c max high gain: 400 v/mv min outstanding cmr: 106 db min industry standard 8-pin dual pinout available in die form general description the op271 is a unity-gain stable monolithic dual op amp featuring excellent speed, 8.5 v/ m s typical, and fast settling time, 2 m s typical to 0. 01%. the op271 has a gain bandw idth of 5 mhz with a high phase margin of 62 . input offset voltage of the op271 is under 200 m v with input offset voltage drift below 2 m v/ c, guaranteed over the full military temperature range. open-loop gain exceeds 400,000 into a 10 k w load ensuring outstanding gain accuracy and linearity. the input bias current is under 20 na limiting errors due to source resistance. the op271? outstanding cmr, over 106 db, and low psrr, under 5.6 m v/v, reduce errors caused by ground noise and power supply fluctua tions. in addition, the op27l exhibits high cmr and psrr over a wide frequency range, further improving system accuracy. figure 1. simplified schematic (one of the two amplifiers is shown.) +in ?in v? out v+ bias obsolete
rev. a ? op271?pecifications (v s = 15 v, t a = 25 c, unless otherwise noted.) electrical characteristics op271a/e op271f op271g parameter symbol conditions min typ max min typ max min typ max unit input offset voltage v os 75 200 150 300 200 400 m v input offset current i os v cm = 0 v 1 10 4 15 7 20 na input bias current i b v cm = 0 v 4 20 6 40 12 60 na input noise voltage density e n f o = 1 khz 7.6 7.6 7.6 nv/hz large-signal v o = 10 v voltage a vo r l = 10 k w 400 650 300 500 250 400 v/mv gain r l = 2 k w 300 500 200 300 175 250 v/mv input voltage range ivr 12 12.5 12 12.5 12 12.5 v output voltage swing v o r l 2 k w 12 13 12 13 12 13 v common-mode rejection cmr v cm = 12 v 106 120 100 115 90 105 db power supply rejection psrr v s = 4.5 v 0.6 3.2 1.8 5.6 2.4 7.0 m v/v ratio to 18 v slew rate sr 5.5 8.5 5.5 8.5 5.5 8.5 v/ m s phase margin u m a v = +1 62 62 62 degrees supply current (all amplifiers) i sy no load 4 5 6.5 4.5 6.5 4.5 6.5 ma gain bandwidth product gbw 5 5 5 mhz channel cs v o = 20 v p-p 125 175 125 175 175 db separation f o = 10 hz 125 175 125 175 175 db input capacitance c in 333p f input resistance differential- mode r in 0.4 0.4 0.4 mw input resistance common mode r incm 20 20 20 g w settling time t s av = +1, 10 v step to 0.01% 2 2 2 m s notes 1 guaranteed by cmr test. 2 guaranteed but not 100% tested. obsolete
rev. a ? op271 electrical characteristics op271a parameter symbol conditions min typ max unit input offset voltage v os 115 400 m v average input offset voltage drift tcv os 0.4 2 m v/ c input offset current i os v cm = 0 v 1.5 30 na input bias current ib v cm = 0 v 7 60 na large-signal voltage a vo v o = 10 v gain r l = 10 k w 300 600 v/mv r l = 2 k w 200 500 v/mv input voltage range 1 ivr 12 12.5 v output voltage swing v o r l 2 k w 12 13 v common-mode rejection cmr v cm = 12 v 100 120 db power supply rejection ratio psrr v s = 4.5 v to 18 v 1.0 5.6 m v/v supply current (all amplifiers) i sy no load 5.3 75 ma note 1 guaranteed by cmr test. electrical characteristics op271a/e op271f op271g parameter symbol conditions min typ max min typ max min typ max unit input offset voltage v os 100 330 215 560 300 700 m v average input offset voltage drift tcv os 0.4 2 1 4 2.0 5 m v/ c input offset current i os v cm = 0 v 1 30 5 40 15 50 na input bias current i b v cm = 0 v 6 60 10 70 15 80 na large-signal a vo v o = 10 v voltage gain r l = 10 k w 300 600 200 500 150 400 v/mv r l = 2 k w 200 500 100 400 90 300 v/mv input voltage range 1 ivr 12 12.5 12 12.5 12 12.5 v output voltage swing v o r l 2 k w 12 13 12 13 12 13 v common-mode rejection cmr v cm = 12 v 100 120 94 115 90 100 db power supply rejection psrr v s = 4.5 v 0.7 5.6 51.8 10 2.0 15 m v/v ratio to 18 v supply current (all amplifiers) i sy no load 5.2 7.2 5.2 7.2 5.2 7.2 ma note 1 guaranteed by cmr test. (v s = 15 v, ?5 c t a 125 c for op271a, unless otherwise noted.) (v s = 15 v, ?0 c t a +85 c, unless otherwise noted.) obsolete
rev. a op271 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op271 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device (continued from page 1) the op271 offers outstanding dc and ac matching between chan- nels. this is especially valuable for applications such as multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters. the op271 conforms to the industry standard, 8-pin dual op amp pinout. it is pin compatible with the tl072, tl082, lf412, and 1458/1558 dual op amps and can be used to significantly improve systems using these devices. for applications requiring lower voltage noise, see the op270. for a quad version of the op271, see the op471. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . 1.0 v differential input current 2 . . . . . . . . . . . . . . . . . . . . 25 ma input voltage . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage output short-circuit duration . . . . . . . . . . . . . . continuous storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . 300 c junction temperature (tj) . . . . . . . . . . . . . ?5 c to +150 c operating temperature range op271a . . . . . . . . . . . . . . . . . . . . . . . . . . . ?5 c to +125 c op271e, op271f, op271g . . . . . . . . . . . ?0 c to +85 c package type ja 3 jc unit 8-pin hermetic dip (z) 134 12 c/w 8-pin plastic dip (p) 96 37 c/w 8-pin soic (s) 92 27 c/w notes 1 absolute maximum ratings apply to packaged parts, unless otherwise noted. 2 the op271? inputs are protected by back-to-back diodes. current limiting resistors are not used in order to achieve low-noise performance. if differential voltage exceeds 1.0 v, the input current should be limited to 25 ma. 3 ja is specified for worst case mounting conditions, i.e., ja is specified for device in socket for cerdip and p-dip packages; ja is specified for device soldered to printed circuit board for soic package. ordering guide package t a = 25 c operating v os max cerdip temperature ( m v) 8-pin plastic range 200 * op271az mil 200 * op271ez xnd 300 * op271fz xnd 400 op271gp xnd 400 * op271gs xnd * not for new design, obsolete april 2002. obsolete
rev. a ? op271 t ypical performance characteristics frequency ? hz voltage noise density ? nv/ hz 3 2 1 1 10 1k 100 4 5 10 20 40 100 t a = 25c v s = 15v 1/f corner = 40hz tpc 1. voltage noise density vs. frequency frequency ? hz current noise density ? pa/ hz 1.0 0.1 10 1k 100 10.0 10k t a = 25c v s = 15v 1/f corner = 40hz tpc 4. current noise density vs. frequency ?75 0 10 8 6 2 4 ?2 temperature ? c input bias current ? na v s = 15v v cm = 0v ?50 ?25 0 25 5 075100125 tpc 7. input bias current vs. temperature supply voltage ? volts 5 0 5 10 t a = 25c voltage noise density ? nv/ hz 15 20 25 10 15 20 at 10hz at 1khz tpc 2. voltage noise density vs. supply voltage temperature ? c input offset voltage ? v 120 0 v s = 15v 100 80 60 40 20 ?20 125100 755025 0 ?25?50?75 tpc 5. input offset voltage vs. temperature ?75 ?50 ?25 0 25 50 75 100 125 0 5 3 1 2 4 ?5 temperature ? c input offset current ? na ?4 ?3 ?2 ?1 tpc 8. input offset current vs. temperature frequency ? hz total harmonic distortion ? % 0.001 10 100 10k 1k 0.01 0.1 t a = 25c v s = 15v v o = 10v p-p r l = 2k a v = 100 a v = 10 a v = 1 tpc 3. total harmonic distortion vs. frequency 0 01 5 234 time ? minutes change in offset voltage ? v t a = 25c v s = 15v 10 9 8 7 6 5 4 3 2 1 tpc 6. warm-up offset voltage drift ?12.5 ?7.5 0?2.5 2.5 7.5 7 6 2 4 3 common mode voltage ? volts input bias current ? na t a = 25c v s = 15v 5 12.5 tpc 9. input bias current vs. common-mode voltage obsolete
rev. a op271 ? 10 1 frequency ? hz cmr ? db 100k 1m 10k 1k 10 100 20 30 40 50 60 70 80 90 100 110 120 130 t a = 25c v s = 15v tpc 10. cmr vs. frequency frequency ? hz psr ? db 0 1 100m 20 140 120 100 80 60 40 10m 1m 100k 10k 1k10010 t a = 25c + psr ?psr tpc 13. psr vs. frequency 0 1 open-loop gain ? db 5 25 20 15 10 10 ?10 t a = 25c v s = 15v 8765432 ?5 phase shift ? deg 100 120 140 160 180 frequency ? mhz phase gain phase margin = 62 c tpc 16. open-loop gain, phase shift vs. frequency supply voltage ? volts total supply current ? ma 7 6 3 0 5 20 10 15 5 4 t a = +125c t a = +25c t a = ?55 c tpc 11. total supply current vs. supply voltage frequency ? hz open-loop gain ? db 140 0 110 100m 120 100 80 60 40 20 10m1m100k10k1k100 t a = 25c v s = 15v tpc 14. open-loop gain vs. frequency 0 open-loop gain ? v/mv 20 t a = 25c r l = 10k 500 supply voltage ? volts 15 10 5 0 1000 1500 2000 tpc 17. open-loop gain vs. supply voltage temperature ? c total supply current ? ma 7 3 125 5 4 6 1007550 25 0 ?25?50?75 v s = 15v tpc 12. total supply current vs. temperature frequency ? hz closed-loop gain ? db 0 80 60 40 20 10m 1m 100k 10k 1k ?20 t a = 25c v s = 15v tpc 15. closed-loop gain vs. frequency 40 v s = 15v temperature ? c phase margin ? deg 125100 7550 25 0 ?25?50?75 gain-bandwidth product ? mhz 150 50 60 70 80 0 2 4 6 8 gbw m tpc 18. gain-bandwidth product, phase margin vs. temperature obsolete
rev. a ? op271 frequency ? hz peak-to-peak amplitude ? volts 4 20 16 12 8 10m 1m 100k 10k 1k 0 t a = 25c v s = 15v thd = 1% r l = 10k 24 28 tpc 19. maximum output swing vs. frequency 20 0 6 load resistance ? maximum output ? volts 4 10 16 12 8 2 14 18 100 10k 1k t a = 25c v s = 15v positive swing negative swing tpc 20. maximum output voltage vs. load resistance 0 20 120 60 100 80 40 frequency ? hz output impedance ? 100 10k 1k t a = 25c v s = 15v a v = 100 100k 1m 10m 140 160 180 a v = 1 tpc 21. output impedance vs. frequency 6 9 8 7 10 12 11 temperature ? c slew rate ? v/s ?75 v s = 15v ?sr +sr ?50 ?25 0 25 50 75 100 125 tpc 22. slew rate vs. temperature 70 frequency ? hz channel separation ? db 100k 1m 10k1k 10 100 80 90 100 160 170 180 190 t a = 25c v s = 15v 110 120 130 140 150 10m tpc 23. channel separation vs. frequency 5 s 5v t a = 25c v s = 15v a v = +1 tpc 24. large-signal transient response 200ns 50mv t a = 25c v s = 15v a v = +1 tpc 25. small signal transient response obsolete
rev. a op271 ? 1/2 op271e a2 assume: a1 and a2 are matched. a o (s) = s v o = (k 1 +1) v in v in v 2 r2 r1 v o 1/2 op271e a1 r2 k1 r2 = r1 r1 k1 op271 r1 8.5v/s place supply decoupling capacitors at op271 v out c l 1000pf v in v+ v? c2 10f c3 0.1f r2 r3 50 r1 + + c1 200pf c4 10f c5 0.1f op271 figure 2. driving large capacitive loads figure 3. pulsed operation application information capacitive load driving and power supply considerations the op217 is u nity -gain stable and is capable of driving large capacitive loads without oscillating. nonetheless, good supply bypassing is highly recommended. proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the op271. in the standard feedback amplifier, the op amp? output resistance combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. a simple circuit to eliminate this effect is shown in figure 2. the added components, c1 and r3, decouple the amplifier from the load capacitance and provide additional stability. the values of c1 and r3 shown in figure 8 are for a load capacitance of up to 1000 pf when used with the op271. unity-gain buffer applications when r f 100 and the input is driven with a fast, large-signal pulse (>1 v), the output waveform will look as shown in figure 3. during the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. with r f 500 , the output is capable of handling the current requirements (i l 20 ma at 10 v); the amplifier will stay in its active mode and a smooth transition will occur. when r f > 3 k , a pole created by r f and the amplifier? input capacitance (3 pf) creates additional phase shift and reduces phase margin. a small capacitor in parallel with r f helps eliminate this problem. computer simulations many electronic design and analysis programs include models for op amps which calculate ac performance from the location of poles and zeros. as an aid to designers utilizing such a program, major poles and zeros of the op271 are listed below. their location will vary slightly between production lots. typically, they will be within 15% of the frequency listed. use of this data will enable the designer to evaluate gross circuit performance quickly, but should not supplant rigorous characterization of a breadboard circuit. poles zeros 15hz 2.5 mhz 1.2 mhz 4 x 23 mhz 2 x 32 mhz - 8 x 40 mhz - applications low phase error amplifier the simple amplifier depicted in figure 4, utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared to conventional amplifier designs. at a given gain, the frequency range for a specified phase accuracy is over a decade greater than for a standard single op amp amplifier. the low phase error amplifier performs second-order frequency compensation through the response of op amp a2 in the feedback loop of a1. both op amps must be extremely well matched in frequency response. at low frequencies, the a1 feedback loop forces v 2 /(k1 + 1)=v in . the a2 feedback loop forces v o /v in =k1 + 1. the dc gain is determined by the resistor divider around a2. note that, like a conventional single op amp amplifier, the dc gain is set by resistor ratios only. minimum gain for the low phase error amplifier is 10. figure 4. low phase error amplifier obsolete
rev. a op271 ? frequency ratio ? 1/ / phase shift ? deg ?7 0.001 0 0.01 0.005 0.005 0.1 1.0 0.5 ?6 ?5 ?4 ?3 ?2 ?1 single op amp, conventional design cascaded (two stages) low phase error amplifier 1/2 op271fz 1/2 op271fz v in i out 11ma r3 10k r1 10k i out = v in rs v in 100 = = 10ma/v r5 100 r2 10k +15v ?15v r4 10k 1 2 3 4 5 6 7 8 v out a r fb b v dd ?15v 0.1f agnd 10pf 10f v out b +15v 10f 0.1f 10pf i out a i out b r fb a dgnd 5v 10v v ref a v ref b dac a/dac b ldac wr dac control reference voltage dac-8222ew dac a dac b 1/2 op271ez 1/2 op271ez 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 4 2 3 + + ? ? 12-bit databus pins 6?17 figure 5. phase error comparison figure 5 compares the phase error performance of the low phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. the low phase error amplifier shows a much lower phase error, particularly for frequencies where t <0.1. for example, phase error of -0.1 occurs at 0.002 t for the single op amplifier, but at 0.11 t for the low phase error amplifier. for more detailed information on the low phase error amplifier, see application note an-107. figure 6. dual 12-bit voltage output dac dual 12-bit voltage output dac the dual voltage output dac shown in figure 6 will settle to 12-bit accuracy from zero to full scale in 2 s typically. the cmos dac-8222 utilizes a 12-bit, double-buffered input structure allowing faster digital throughput and minimizing digital feedback. fast current pump maximum output current of the fast current pump shown in figure 7 is 11 ma. voltage compliance exceeds 10 v with 15 v supplies. the current pump has an output resistance of over 3 m and maintains 12-bit linearity over its entire out put range. figure 7. fast current pump obsolete
rev. a op271 ?0 8-lead ceramic dip-glass hermetic seal [cerdip] (q-8) dimensions shown in inches and (millimeters) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inch; millimeters dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design outline dimensions 8-lead plastic dual-in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeters dimensions (in parentheses) compliant to jedec standards mo-095aa 8-lead standard small outline package [soic] narrow body (rn-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa obsolete
rev. a op271 ?1 revision history location page 10/02data sheet changed from rev. 0 to rev. a. deleted pin connections caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 obsolete
?2 c00326-0-10/02(a) printed in u.s.a. obsolete

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